VLSI Technology (Course Code: 4353206)

Gujarat Technological University (GTU)
Competency-focused Outcome-based Green Curriculum-2021 (COGC-2021)
Semester: V

Program	Semester
Information and Communication Technology (ICT) Diploma	V

1. RATIONALE

This course will provide an opportunity to the ICT students to learn about fundamentals of VLSI Technology such as trends in VLSI, MOSFET structure and Analysis of MOS circuits. In laboratory part of this course, students will be given exposure to develop RTL code for different types of digital circuits. This subject is very important for the students for their career advancement in VLSI field.

2. COMPETENCY

The course content should be taught and implemented with the aim to develop required skills in the students so that they are able to acquire following competency:

Circuit design using MOS transistors
Develop and test Verilog programs for VLSI based electronic circuits.

3. COURSE OUTCOMES (COs)

Describe various VLSI design style, Design methodology, Design flow.
Understand structure and working of MOSFET and Scaling.
Understand characteristics of MOS inverter circuits for different load.
Design of combinational and sequential circuits using MOSFET.
Develop Verilog code for combinational and sequential design.

4. TEACHING AND EXAMINATION SCHEME

Teaching Scheme (Hours)			Credits	Theory Marks		Practical Marks		Total
L	T	P	C	CA	ESE	CA	ESE	Marks
3	0	2	4	70	30*	25	25	150

Note: Out of 30 marks under the theory CA, 10 marks are for assessment of the micro-project to facilitate integration of COs and the remaining 20 marks is the average of 2 tests to be taken during the semester for assessing the attainment of the cognitive domain UOs required for the attainment of the COs.

Legends: L - Lecture; T - Tutorial/Teacher Guided Theory Practice; P - Practical; C - Credit; CA - Continuous Assessment; ESE - End Semester Examination

5. SUGGESTED PRACTICAL EXERCISES

The following practical outcomes (PrOs) are the subcomponents of the Course Outcomes (COs). Some of the PrOs marked '*' are compulsory, as they are crucial for that particular CO at the 'Precision Level' of Dave's Taxonomy related to 'Psychomotor Domain'.

Sr. No.	Practical Outcomes (PrOs)	Unit No.	Approx. Hrs. Required
1.	Identify Verilog modules and coding styles in Verilog	V	2
2.	Simulate the Basic logic gates using Verilog	IV, V	2
3.	Simulate universal gates using Verilog	IV, V	2
4.	Simulate XOR and XNOR using Verilog	IV, V	2
5.	Simulate Half adder using Verilog	IV, V	2
6.	Simulate full adder using half adder in Verilog	IV, V	2
7.	Simulate four bit adder using Verilog	IV, V	2
8.	Simulate 4 x1 multiplexer using Verilog	IV, V	2
9.	Simulate 1 x 4 de-mux using Verilog	IV, V	2
10.	Simulate 3:8 decoder using Verilog	IV, V	2
11.	Simulate 8:3 encoder using Verilog	IV, V	2
12.	Simulate Parity generator and checker using Verilog	IV, V	2
13.	Simulate flip-flops (SR, D, T, JK) using Verilog	IV, V	2
14.	Simulate 4 bit Up counter using Verilog	IV, V	2
15.	Simulate 4 bit shift register using Verilog	IV, V	2
16.	Verify digital circuits by implementing testbench for it in Verilog	IV, V	2
17.	Hardware implementation of above programs	I, IV, V	2
	Total		34 Hrs

Notes:

More Practical Exercises can be designed and offered by the respective course teacher to develop the industry relevant skills/outcomes to match the COs. The above table is only a suggestive list
Perform any of the practical exercises for a total of minimum 28 hours from above list depending upon the availability of resources so that skills matching with the most of the outcomes in every unit is included

6. MAJOR EQUIPMENT/ INSTRUMENTS REQUIRED

Sr. No.	Equipment Name with Broad Specifications	PrO. No.
1	Computer System	ALL
2	Verilog Simulator Software	ALL
3	VLSI Trainer Kits	ALL

Software/Learning Websites

ISE Simulator
QUARTUS-II-ALTERA EVAL VERSION
Modalism® HDL simulator for use by students in their academic coursework
EDA Playground
Amrita Virtual Labs - VLSI

7. AFFECTIVE DOMAIN OUTCOMES

The following sample Affective Domain Outcomes (ADOs) are embedded in many of the above-mentioned COs and PrOs. More could be added to fulfill the development of this competency.

Work as a leader/a team member
Follow ethical practices

8. UNDERPINNING THEORY

Only the major Underpinning Theory is formulated as higher level UOs of Revised Bloom's taxonomy in order development of the COs and competency is not missed out by the students and teachers. If required, more such higher level UOs could be included by the course teacher to focus on attainment of COs and competency.

Unit	UO	Unit Outcomes (4 to 6 UOs at Application and above level)	Topics and Sub-topics
Unit-I: Introduction to VLSI	1a	Describe Overview of VLSI Design Methodologies, VLSI design flow	1.1 VLSI design Methodology, Time to Market, Major Constraints for chip designing, ASIC Design flow 1.2 Y-Chart
	1b	Explain Design Hierarchy, Concept of Regularity, Modularity and Locality	1.3 Concept of Top-Down, Bottom-Up approach 1.4 Regularity, modularity, locality
	1c	Explain VLSI Design styles: Full Custom, Semi-Custom	1.5 Overview of FPGA, Gate Array Design, Standard Cell Based Design, Full Custom Design
Unit-II: MOS Transistor	2a	Explain MOSFET structure and its working under different bias conditions	2.1 Energy band Diagram and Structure of MOS 2.2 The MOS System under External Bias
	2b	Explain Operation of MOS Transistor (MOSFET) and voltage-current characteristics	2.3 Channel formation 2.4 Symbols for different MOSFET 2.5 MOSFET Current-Voltage characteristics 2.6 Gradual channel Approximation
	2c	Explain MOSFET Scaling	2.7 Needs of scaling 2.8 Full-Voltage Scaling, Constant-Voltage Scaling 2.9 Effect of Scaling
Unit-III: MOS Inverters	3a	Describe Basics of MOSFET inverter	3.1 Concept and working of Ideal Inverter 3.2 Noise Margin 3.3 Voltage Transfer Characteristics
	3b	Describe Resistive load Inverter	3.4 Working and VTC without derivation
	3c	Differentiate Inverter with n-type MOSFET load (Enhancement & Depletion type MOSFET load)	3.5 Working and VTC without derivation for Enhancement & Depletion type MOSFET load
	3d	Explain CMOS Inverter and its characteristics	3.6 Working and VTC without derivation for CMOS inverter
Unit-IV: MOS Circuits	4a	Explain two input NAND and NOR Gate with depletion NMOS load	4.1 MOS logic circuits with Depletion nMOS Loads
	4b	Explain Two input NAND and NOR Gate using CMOS logic	4.2 CMOS logic circuits 4.3 Stick Diagram 4.4 Euler path Approach
	4c	Differentiate AOI and OAI Logic. Design simple XOR function	4.5 Complex logic circuits
	4d	Describe the working of SR latch circuit. Distinguish Clocked latch and Flip-Flop circuit	4.6 The SR latch circuit 4.7 Clocked latch and Flip-flop circuit 4.8 CMOS D-latch and Edge-triggered flip-flop
Unit-V: Verilog Programming	5a	Describe Verilog: HDL fundamentals, simulation, coding style and test-bench design	5.1 Module definition 5.2 RTL coding style: Gate level, Data flow, Behavioral, Mixed approach 5.3 Stimulus generation
	5b	Develop Verilog Programs related to basic logic gates	5.4 Basic Logic gate implementation in Verilog
	5c	Develop Verilog Programs related to Fundamental Arithmetic operations	5.5 Verilog code for adder and subtractor circuits
	5d	Develop Verilog Programs related to Combinational circuits	5.6 Combinational circuits: Multiplexer, Demultiplexer, Decoder and Encoder, Parity Generator and parity checker
	5e	Develop Verilog Programs related to Sequential circuits	5.7 Basic Sequential circuits: SR latch, D F/F, T F/F, JK F/F 5.8 Parallel input Parallel output Shift Register, Up Counter, Down Counter

9. SUGGESTED SPECIFICATION TABLE FOR QUESTIONPAPER DESIGN

Unit	Unit Title	Teaching Hours	Distribution of Theory Marks			Total
			R Level	U Level	A Level	Marks
1	Introduction to VLSI	6	2	6	6	10
2	MOS Transistor	8	4	8	2	14
3	MOS Inverters	6	5	5	2	12
4	MOS Circuits	10	2	6	10	18
5	Verilog Programming	12	2	2	12	16
Total		42	18	22	30	70

10. SUGGESTED STUDENT ACTIVITIES

Other than the laboratory learning, following are the suggested student-related cocurricular activities which can be undertaken to accelerate the attainment of the various outcomes in this course: Students should conduct following activities in group and prepare reports of each activity.

Prepare chart to represent the CMOS design process
Prepare chart to represent the technological advancements in CMOS technology starting from transistors to current technology
Project- Build a small ASIC for your Home /Community.
Prepare chart showing the types of FPGA technology
List out methods used in industries for each step used in CMOS design process.

These are sample strategies, which the teacher can use to accelerate the attainment of the various outcomes in this course:

Show Video/Animation film explaining VLSI Design which are available on internet
Arrange expert lecture on VHDL programming for real life applications
Massive open online courses (MOOCs) may be used to teach various topics/sub topics
Guide students for using latest Technical Magazine
Visit industries where equipment/gadgets using VLSI are being manufactured/assembled
Guide student(s) in undertaking micro-projects

11. SUGGESTED SPECIAL INSTRUCTIONAL STRATEGIES

Only one micro-project is planned to be undertaken by a student that needs to be assigned to him/her in the beginning of the semester. In the first four semesters, the micro-project is group-based. However, in the fifth and sixth semesters, it should be preferably be individually undertaken to build up the skill and confidence in every student to become problem solver so that s/he contributes to the projects of the industry. In special situations where groups have to be formed for micro-projects, the number of students in the group should not exceed three.

The micro-project could be industry application based, internet-based, workshop-based, laboratory-based or field-based. Each micro-project should encompass two or more COs which are in fact, an integration of PrOs, UOs and ADOs. Each student will have to maintain dated work diary consisting of individual contribution in the project work and give a seminar presentation of it before submission. The total duration of the micro-project should not be less than 16 (sixteen) student engagement hours during the course. The student ought to submit micro-project by the end of the semester to develop the industry-oriented COs.

A suggestive list of micro-projects is given here. This has to match the competency and the COs. Similar micro-projects could be added by the concerned course teacher.

12. SUGGESTED PROJECT LIST

MICRO PROJECT 1: Prepare following Items

Prepare graph showing relationship between feature size, number of transistors and year (Silicon Roadmap)
Prepare graph showing various design methodology

MICRO PROJECT 2: Design Application oriented basic Project using FPGA

Design and Implement LED flasher circuit
Design and Implement circuit for relay-based operation using switch
Design and Implement Room Temperature Monitor/Controller System
Design and Implement Water Level Indicator/controller circuit

MICRO PROJECT 3: Prepare following Items

Prepare chart indicating the types of etching processes used with its application
Prepare chart indicating the deposition processes with its application
Prepare a survey report on the types of transistors used in memory elements
Prepare a survey report on requirements of clean room and its classification

13. SUGGESTED LEARNING RESOURCES

Sr. No.	Title of Book	Author	Publication
1	CMOS DIGITAL INTEGRATED CIRCUITS	Sung Mo Kang	TMH
2	Introduction to VLSI Circuits and Systems	Uyemura J.P.	WILEY INDIA PVT. LTD.
3	VLSI DESIGN	Das Debaprasad	OXFORD
4	VLSI DESIGN Theory and Practice	Vij Vikrant, Er. Syal Nidhi	LAXMI PUBLICATIONS PVT. LTD.
5	CMOS Circuit Design, Layout, and Simulation	Baker, Li, Boyce	Wiley
6	Verilog HDL: A Guide to Digital design and Synthesis	Samir Palnitkar	SunSoft Press
7	A Verilog HDL Primer	Bhasker (J).	Bsp Professional Books

14. SOFTWARE/LEARNING WEBSITES

15. PO-COMPETENCY-CO MAPPING

Program Outcomes (POs):

PO1 - Basic & Discipline specific knowledge: Apply knowledge of basic mathematics, science and engineering fundamentals and engineering specialization to solve the engineering problems.

PO2 - Problem Analysis: Identify and analyze well defined engineering problems using codified standard methods.

PO3 - Design/Development of Solution: Design solutions for well-defined technical problems and assist with the design of systems, components or processes to meet specified needs.

PO4 - Engineering Tools, Experimentation and Testing: Apply modern engineering tools and relevant technique to conduct standard tests and measurements.

PO5 - Engineering practices for Society, Environment and sustainability: Apply relevant technology in context of Society, sustainability, environment and ethical practices.

PO6 - Project Management: Use engineering management principles individually, as a team member or a leader to manage projects and effectively communicate about well-defined engineering activities.

PO7 - Life-long learning: Ability to analyze individual needs and engage in updating in the context of technological changes.

Competency: Circuit design using MOS transistors and Develop and test Verilog programs for VLSI based electronic circuits.

Course Outcomes	PO1	PO2	PO3	PO4	PO5	PO6	PO7
CO1: Describe various VLSI design style, Design methodology, Design flow	3	2	2	3	2	3	3
CO2: Understand structure and working of MOSFET, MOSFET Geometry Scaling	3	3	2	1	1	2	3
CO3: Understand the working and characteristics of MOS inverter circuits for different load	3	2	3	2	2	2	3
CO4: Design of combinational and sequential circuits using MOSFET	3	3	3	2	2	2	2
CO5: Develop Verilog code for combinational and sequential design	2	3	3	3	3	3	2

Legend: '3' for high, '2' for medium, '1' for low and '-' for no correlation of each CO with PO.

16. COURSE CURRICULUM DEVELOPMENT COMMITTEE

GTU Resource Persons

Sr. No.	Name and Designation	Institute	Contact No.	Email
1	GIREEJA DINESHCHANDRA AMIN	GGP, AHMEDABAD	7574850311	gireeja.amin@gmail.com